Make

A program builder that uses Makefile for instructions. Often used as a task runner.

Notes:

A target is out-of-date if it is older than any of its prerequisites.
The first non-special target is run if no target is specified.
The $@ macro expands to the target name.
The $< macro expands to the first prerequisite.
@ before a command stops it from being printed.
Each command is run in a new shell.
The default shell is /bin/sh (can be changed with the SHELL macro).
Macros can be overwritten with arguments in the key=value form, e.g. make CC=gcc.

Stick to the POSIX standard.
Add .POSIX: to the top of the Makefile to get reliable POSIX behavior.
Add .SUFFIXES: to the top of the Makefile to clear the builtin C rules.
Add .PHONY: to non-file targets such as clean (non-POSIX).
Use = to define macros and $() to expand them.
Use macro name conventions:
- CC - compiler to use
- CFLAGS - compiler flags
- LDFLAGS - linker flags
- LDLIBS - libraries to link